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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9218 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 functional block diagram 10-bit, 40/65/80/105 msps 3 v dual a/d converter functional block diagram timing adc output register ref t/h 10 10 adc output register t/h 10 10 timing user select #1 user select #2 data format/ gain d 9b ? 0b d 9a ? 0a v dd gnd v d ad9218 encode a encode b a in b a in a a in a ref in a ref in b ref out a in b features dual 10-bit, 40 msps, 65 msps, 80 msps, and 105 msps adc low power: 275 mw at 105 msps per channel on-chip reference and track/holds 300 mhz analog bandwidth each channel snr = 57 db @ 41 mhz, encode = 80 msps 1 v p-p or 2 v p-p analog input range each channel single 3.0 v supply operation (2.7 vC3.6 v) power-down mode for single channel operation twos complement or offset binary output mode output data alignment mode pin-compatible with 8-bit ad9288 C75 dbc crosstalk between channels applications battery-powered instruments hand-held scopemeters low cost digital oscilloscopes i and q communications ultrasound equipment general description the ad9218 is a dual 10-bit monolithic sampling analog-to- digital converter with on-chip track-and-hold circuits and is optimized for low cost, low power, small size and ease of use. the product operates at a 105 msps conversion rate with outstanding dynamic performance over its full operating range. each channel can be operated independently. the adc requires only a single 3.0 v (2.7 v to 3.6 v) power supply and an encode clock for full operation. no external reference or driver components are required for many applica- tions. the digital outputs are ttl/cmos-compatible and a separate output power supply pin supports interfacing with 3.3 v or 2.5 v logic. the clock input is ttl/cmos-compatible and the 10-bit digital outputs can be operated from 3.0 v (2.5 v to 3.6 v) supplies. user-selectable options are available to offer a combi- nation of power-down modes, digital data formats and digital data timing schemes. in power-down mode, the digital outputs are driven to a high-impedance state. fabricated on an advanced cmos process, the ad9218 is available in a 48-lead surface-mount plastic package (7 7 mm lqfp) specified over the industrial temperature range (?0 c to +85 c). product highlights low power?ust 275 mw power dissipation per channel at 105 msps. other speed grade proportionally scaled down while maintaining high ac performance. pin compatibility upgrade?llows easy migration from 8-bit to 10-bit. pin-compatible with the 8-bit ad9288 dual adc. ease of use?n-chip reference and user controls provide flex- ibility in system design. high performance?aintain 54 db snr at 105 msps with a nyquist input. channel crosstalk?ery low at ?5 dbc.
rev. 0 C2C ad9218?pecifications dc specifications test ad9218bst-40/-65 ad9218bst-80/-105 parameter temp level min typ max min typ max unit resolution 10 10 bits accuracy no missing codes 1 full vi gnt gnt offset error 2 25 c i ?8 2 18 ?8 2 18 lsb gain error 2 25 c i ? 3 8 ? 3.5 8 % fs differential nonlinearity 25 ci 1 0.3/ 0.6 1/1.3 ? 0.5/ 0.8 1.2/1.7 lsb (dnl) full vi 0.8 0.6/ 0.9 lsb integral nonlinearity (inl) 25 c i ?/?.6 0.3/ 1 1/1.6 ?.35/?.7 0.75/ 2 1.35/2.7 lsb full vi 1 1/ 2.3 lsb temperature drift offset error full v 10 4 ppm/ c gain error 2 full v 80 100 ppm/ c reference full v 40 40 ppm/ c reference internal reference voltage 25 c i 1.18 1.24 1.28 1.18 1.24 1.28 v (refout) input resistance (refin a, b) full v 9 11 13 9 11 13 k ? analog inputs differential input voltage full v 1 or 2 1 v range (ain, ain ) 3 common-mode voltage full v v d /3 v d /3 v input resistance full vi 8 10 14 8 10 14 k ? input capacitance 25 cv 3 3 pf power supply v d full iv 2.7 3 3.6 2.7 3 3.6 v v dd full iv 2.7 3 3.6 2.7 3 3.6 v supply currents iv d (v d = 3.0 v) 4 full vi 108/117 113/122 172/183 175/188 ma iv dd (v dd = 3.0 v) 4 25 c v 7/11 13/17 ma power dissipation dc 5 full vi 325/350 340/365 515/550 525/565 mw iv d power-down current 6 full vi 20 22 ma power supply rejection ratio 25 ci 1 1 mv/v notes 1 no missing codes across industrial temperature range guaranteed for -40 msps, -65 msps, and -80 msps grades. no missing codes a t room temperature guaran- teed for -105 grade. 2 gain error and gain temperature coefficients are based on the adc only (with a fixed 1.25 v external reference) -65 grade in 2 v p-p range, -40, -85, -105 grades in 1 v p-p range. 3 (ain ? ain ) = 0.5 v in 1 v range (full scale), (ain ? ain ) = 1 v in 2 v range (full scale). 4 ac power dissipation measured with rated encode and a 10.3 mhz analog input @ 0.5 dbfs, c load = 5 pf. 5 dc power dissipation measured with rated encode and a dc analog input (outputs static, iv dd = 0) 6 in power-down state iv dd = 10 a typical (all grades). specifications subject to change without notice. (v dd = 3.0 v, v d = 3.0 v; external reference, unless otherwise noted.)
rev. 0 C3C ad9218 digital specifications test ad9218bst-40/-65 ad9218bst-80/-105 parameter temp level min typ max min typ max unit digital inputs encode input common mode full v v d /2 v d /2 v encode ??voltage full vi 2 2 v encode ??voltage full vi 0.8 0.8 v encode input resistance full vi 1.8 2.0 2.3 1.8 2.0 2.3 k ? logic ??voltage?1, s2, dfs full vi 2 2 v logic ??voltage?1, s2, dfs full vi 0.8 0.8 v logic ??current?1 full vi 50 10 +50 50 10 +50 a logic ??current?1 full vi ?00 ?30 ?0 ?00 ?30 ?0 a logic ??current?2 full vi 50 230 400 50 230 400 a logic ??current?2 full vi 50 10 +50 50 10 +50 a logic ??current?fs full vi 30 100 200 30 100 200 a logic ??current?fs full vi ?00 ?30 ?0 ?00 ?30 ?0 a input capacitance?1, s2, encode inputs 25 cv 2 2 pf input capacitance dfs 25 c v 4.5 4.5 pf digital outputs logic ??voltage full vi 2.45 2.45 v logic ??voltage full vi 0.05 0.05 v output coding two? comp. or offset binary two? comp. or offset binary specifications subject to change without notice. ac specifications test ad9218bst-40/-65 ad9218bst-80/-105 parameter temp level min typ max min typ max unit dynamic performance 1 signal-to-noise ratio (snr) (without harmonics) f in = 10.3 mhz 25 c i 58/55 59/57 57/53 58/55 db f in = nyquist 2 25 c i -/54 59/56 55/52 57/54 db signal-to-noise ratio (sinad) (with harmonics) f in = 10.3 mhz 25 c i 58/54 59/56 56/52 58/53 db f in = nyquist 2 25 c i -/53 59/55 55/51 57/53 db effective number of bits f in = 10.3 mhz 25 c i 9.4/8.8 9.6/9.1 9.1/8.4 9.4/8.6 bits f in = nyquist 2 25 c i -/8.6 9.6/8.9 9/8.3 9.3/8.6 bits second harmonic distortion f in = 10.3 mhz 25 c i ?2/?6 89/77 ?9/?0 ?7/?8 dbc f in = nyquist 2 25 c i -/?3 89/72 ?5/?7 ?6/?6 dbc third harmonic distortion f in = 10.3 mhz 25 c i ?8/?2 79/68 ?2/?7 ?1/?3 dbc f in = nyquist 2 25 c i -/?0 78/64 ?3/?7 ?3/?9 dbc spurious free dynamic range sfdr f in = 10.3 mhz 25 c i ?8/?2 79/67 ?2/?7 ?9/?2 dbc f in = nyquist 2 25 c i -/?0 78/64 ?3/?7 ?0/?3 dbc two-tone intermod distortion (imd) f in1 = 10 mhz, f in2 = 11 mhz 25 c v ?4/?3 dbc at ? dbfs f in1 = 30 mhz, f in2 = 31 mhz 25 c v ?3/?3 ?7/?7 dbc at ? dbfs analog bandwidth, full power 25 c v 300 300 mhz crosstalk 25 c v ?5 ?5 dbc notes 1 ac specs based on an analog input voltage of ?.5 dbfs at 10.3 mhz unless otherwise noted. ac specs for -40, -80, -105 grades a re tested in 1 v p-p range and driven differentially. ac specs for -65 grade are tested in 2 v p-p range and driven differentially. 2 the -65, -80, and -105 grades are tested close to nyquist for that grade: 31 mhz, 39 mhz, and 51 mhz for the -65, -80, and -105 grades respectively. specifications subject to change without notice. (v dd = 3.0 v, v d = 3.0 v; external reference, unless otherwise noted.) (v dd = 3.0 v, v d = 3.0 v; external reference, unless otherwise noted.)
rev. 0 C4C ad9218?pecifications switching specifications test ad9218bst-40/-65 ad9218bst-80/-105 parameter temp level min typ max min typ max unit encode input parameters maximum encode rate full vi 40/65 80/105 msps minimum encode rate full iv 20/20 20/20 msps encode pulsewidth high (t eh ) full iv 7/6 5/3.8 ns encode pulsewidth low (t el ) full iv 7/6 5/3.8 ns aperture delay (t a )25 cv 2 2 ns aperture uncertainty (jitter) 25 c v 3 3 ps rms digital output parameters output valid time (t v ) * full vi 3 3 ns output propagation delay (t pd ) * full vi 4.5 7 4.5 6 ns output rise time (t r )25 c v 1 1.0 ns output fall time (t f )25 c v 1.2 1.2 ns out of range recovery time 25 cv 5 5 ns transient response time 25 cv 5 5 ns recovery time from power-down 25 c v 10 10 cycles pipeline delay full iv 5 5 cycles notes * t v and t pd are measured from the 1.5 level of the encode input to the 50%/50% levels of the digital outputs swing. the digital output loa d during test is not to exceed an ac load of 5 pf or a dc current of 40 a. rise and fall times measured from 10% to 90%. specifications subject to change without notice. sample n a in a, a in b encode a&b d 9a d 0a d 9b d 0b data n 5 sample n+1 t pd sample n+2 sample n+3 sample n+4 sample n+5 sample n+6 data n 4 data n 3 data n 2 data n 1 data n data n 5 data n 4 data n 3 data n 2 data n 1 data n t v 1/f s t el t eh t a figure 1. normal operation, same clock (s1 = 1, s2 = 0) channel timing (v dd = 3.0 v, v d = 3.0 v; external reference, unless otherwise noted.)
rev. 0 ad9218 C5C sample n d 9a d 0a d 9b d 0b sample n+1 t pd sample n+2 sample n+3 sample n+4 sample n+5 sample n+6 t v 1/f s t el t eh t a data n 10 data n 8 data n 6 data n 4 data n 2 data n data n+2 data n 9 data n 7 data n 5 data n 3 data n 1 data n+1 encode a encode b a in a, a in b sample n+7 sample n+8 figure 2. normal operation with two clock sources (s1 = 1, s2 = 0) channel timing sample n d 9a d 0a d 9b d 0b sample n+1 t pd sample n+2 sample n+3 sample n+4 sample n+5 sample n+6 t v 1/f s t el t eh t a data n 10 data n 8 data n 6 data n 4 data n 2 data n data n+2 encode a encode b a in a, a in b sample n+7 sample n+8 data n 11 data n 9 data n 7 data n 5 data n 3 data n 1 data n+1 figure 3. data align with two clock sources (s1 = 1, s2 = 1) channel timing
rev. 0 ad9218 C6C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9218 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 v d , v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 v analog inputs . . . . . . . . . . . . . . . . . . . . ?.5 v to v d + 0.5 v digital inputs . . . . . . . . . . . . . . . . . . . ?.5 v to v dd + 0.5 v ref in inputs . . . . . . . . . . . . . . . . . . . . . ?.5 v to v d + 0.5 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature . . . . . . . . . . . . . . . . ?5 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . . 150 c maximum case temperature . . . . . . . . . . . . . . . . . . . . 150 c ja 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 c/w notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. 2 measured on a four-layer board with solid ground plane. explanation of test levels test level i 100% production tested. ii 100% production tested at 25 c and sample tested at speci- fied temperatures. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi 100% production tested at 25 c; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. table i. user select modes s1 s2 user select options 0 0 power-down both channel a and b. 0 1 power-down channel b only. 1 0 normal operation (data align disabled). 1 1 data align enabled (data from both channels available on rising edge of clock a. channel b data is delayed by a 1/2 clock cycle.) ordering guide temperature package model range package description option ad9218bst-40, -65, -80, -105 ?0 c to +85 c metric quad flat pack (1.4 mm thick: lqfp) st-48 ad9218-65pcb 25 c evaluation board (supports -40/-65 grade) AD9218-105PCB 25 c evaluation board (supports -80/-105 grade)
rev. 0 ad9218 C7C pin function descriptions pin no. mnemonic description 1, 12, 16, 27, 29, 32, 34, 45 gnd ground 2a in a analog input for channel a 3 a in a analog input for channel a (complementary) 4 dfs/gain data format select and analog input gain mode. (low = offset binary out- put available, 1 v p-p supported; high = two? complement output available, 1 v p-p supported; floating = off set binary output availab le, 2 v p-p supported; set to v ref = two? complement output available, 2 v p-p supported.) 5 ref in a reference voltage input for channel a 6 ref out internal reference voltage 7 ref in b reference voltage input for channel b 8 s1 user select #1 (refer to table i) 9 s2 user select #2 (refer to table i) 10 a in b analog input for channel b (complementary) 11 a in b analog input for channel b 13, 30, 31, 48 v d analog supply (3 v) 14 enc b clock input for channel b 15, 28, 33, 46 v dd digital supply (2.5 v to 3.6 v) 17?6 d9 b ?0 b digital output for channel b (d9 b = msb) 35?4 d0 a ?9 a digital output for channel a (d9 a = msb) 47 enc a clock input for channel a pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) d1 a d0 a gnd v dd gnd v d v d gnd a in a a in a dfs/gain ref in a ref out ref in b s1 s2 a in b a in b gnd v dd gnd d0 b ad9218 gnd d1 b v d enc a v dd gnd d9 a (msb) d8 a d7 a d6 a d5 a d4 a d3 a d2 a v d enc b v dd gnd (msb) d9 b d8 b d7 b d6 b d5 b d4 b d3 b d2 b
rev. 0 ad9218 C8C terminology analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. crosstalk coupling onto one channel being driven by a low level (?0 dbfs) signal when the adjacent interfering channel is driven by a full-scale signal. differential analog input resistance, differential analog input capacitance and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capaci- tance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential volt age is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. peak-to-peak differential is computed by rotating the inputs phase 180 degrees and again taking the peak measurement. the difference is then computed between both peak measurements. differential nonlinearity the deviation of any code width from an ideal 1 lsb step. effective number of bits the effective number of bits (enob) is calculated from the measured snr based on the equation: enob snr db measured = . . 176 602 encode pulsewidth/duty cycle pulsewidth high is the minimum amount of time that the encode pulse should be left in logic 1 state to achieve rated performance; pulsewidth low is the minimum time encode pulse should be left in low state. see timing implications of changing t ench in text. at a given clock rate, these specif ica- tions define an acceptable encode duty cycle. full-scale input power expressed in dbm. computed using the following equation: power v z full scale full scale rms input ? ? = ? ? ? ? ? ? ? ? ? ? ? ? 10 0 001 2 log . gain error gain error is the difference between the measured and ideal full scale input voltage range of the adc. harmonic distortion, second the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. harmonic distortion, third the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the encode rate at which parametric testing is performed. output propagation delay the delay between a differential crossing of encode and encode and the time when all output data bits are within valid logic levels. noise (for any range within the adc) vz noise fs snr signal dbm dbc dbfs = ?? ? ? ? ? ? ? 0 001 10 10 . where z is the input impedance, fs is the full scale of the device for the frequency in question, snr is the value for the particular input level, and signal is the signal level within the adc reported in db below full scale. this value includes both thermal and quantization noise. power supply rejection ratio the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set 1 db below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious compo- nent may or may not be a harmonic. may be reported in dbc (i.e., degrades as signal level is lowered), or dbfs (always related back to converter full scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. may be reported in dbc (i.e., degrades as signal level is lowered), or in dbfs (always related back to converter full scale).
rev. 0 ad9218 C9C worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dbc. transient response time transient response is defined as the time it takes for the adc to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. out-of-range recovery time out of range recovery time is the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. equivalent circuits a in 40 40 30k 30k 15k 15k v d a in figure 4. analog input stage encode 2.6k 2.6k 600 v d figure 5. encode inputs out v d figure 6. reference output stage v dd 40 dx figure 7. digital output stage ref 10k v d figure 8. reference inputs s2 10k v d '
5 *# s1 10k v d '
( *( dfs/gain 15k 15k vref v d figure 11. dfs/gain input
rev. 0 ad9218 C10C typical performance characteristics 100 0 90 52.5 80 70 60 50 40 30 20 10 0 encode = 105msps a in = 50.1mhz at 0.5dbfs snr = 53.8db sinad = 53.4db h2 = 69db h3 = 65.8db db tpc 1. fft: fs = 105 msps, a in = 50.1 mhz @ C0.5 dbfs, differential, 1 v p-p input range 0 10 20 30 40 50 60 70 80 90 100 db encode = 80msps a in = 39mhz at 0.5dbfs snr = 56.1db sinad = 55.5db h2 = 71.8db h3 = 66.2db 040 tpc 2. fft: fs = 80 msps, a in = 39 mhz @ C0.5 dbfs, differential, 1 v p-p input range encode = 65msps a in = 30.3mhz at 0.5dbfs snr = 56.1db sinad = 55.9db sfdr = 72db h2 = 83.2db h3 = 79db 100 0 90 32.5 80 70 60 50 40 30 20 10 0 db tpc 3. fft: fs = 65 msps, a in = 30.3 mhz @ C0.5 dbfs, differential, 2 v p-p input range 0 10 20 30 40 50 60 70 80 90 100 db encode = 40msps a in = 19.75 mhz at 0.5dbfs snr = 58.4db sinad = 58.3db h2 = 87db h3 = 81db 020 tpc 4. fft: fs = 40 msps, a in = 19.7 mhz @ C0.5 dbfs, differential, 1 v p-p input range 100 0 90 40 80 70 60 50 40 30 20 10 0 encode = 105msps a in = 70mhz at 0.5dbfs snr = 51.9db sinad = 51.8db h2 = 70.5db h3 = 76.3db db tpc 5. fft: fs = 105 msps, a in = 70 mhz @ C0.5 dbfs, differential, 1 v p-p input range encode = 65msps a in = 15mhz at 0.5dbfs snr = 56.4db sinad = 55.9db h2 = 73.9db h3 = 71.7db 0 32.5 100 90 80 70 60 50 40 30 20 10 0 db tpc 6. fft: fs = 65 msps, a in = 15 mhz @ C0.5 dbfs; with ad8138 driving adc inputs, 1 v p-p input range
rev. 0 ad9218 C11C 0 10 20 30 40 50 60 70 80 90 100 db encode = 31msps a in = 8mhz at 0.5dbfs snr = 59.23db sinad = 59.1db h2 = 87db h3 = 81db 0 15.5 tpc 7. fft: fs = 31 msps, a in = 8 mhz @ C0.5 dbfs, differential, 1 v p-p input range a in frequency mhz 30 050 db 2nd 3rd sfdr 35 40 45 50 55 60 65 70 75 80 100 150 200 250 tpc 8. harmonic distortion (second and third) and sfdr vs. a in frequency (1 v p-p, fs = 105 msps) a in frequency mhz 30 050 db 2nd 3rd sfdr 35 40 45 50 55 60 65 70 75 80 100 150 200 250 tpc 9. harmonic distortion (second and third) and sfdr vs. a in frequency (1 v p-p, fs = 80 msps) 0 10 20 30 40 50 60 70 80 90 100 db encode = 31msps a in = 8mhz at 0.5dbfs snr = 59db sinad = 58.8db h2 = 78.7db h3 = 72.9db 0 15.5 tpc 10. fft: fs = 31 msps, a in = 8 mhz @ C0.5 dbfs; with ad8138 driving adc inputs, 1 v p-p input range 100 0 90 52.5 80 70 60 50 40 30 20 10 0 encode = 105msps a in 1 = 30.1mhz at 7dbfs a in 2 = 31.1mhz at 7dbfs sfdr = 67dbfs db 08+(( 0 "0

-$:; $(:;?( > '*.(1:*8*/ 100 0 90 40 80 70 60 50 40 30 20 10 0 encode = 80msps a in 1 = 29.3mhz at 7dbfs a in 2 = 30.3mhz at 7dbfs sfdr = 77dbfs db 08+(# 0 "0

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rev. 0 ad9218 C12C sfdr 1v sfdr 2v h3 2v h2 2v h3 1v h2 1v a in frequency mhz db 0 20 40 60 80 100 120 140 160 180 10 20 30 40 60 70 80 90 50 2v single-ended drive 1v differential drive tpc 13. harmonic distortion (second and third) and sfdr vs. a in frequency (fs = 65 msps) 3rd sfdr a in frequency mhz db 10 20 30 40 50 60 70 90 85 80 75 70 65 60 55 50 2nd tpc 14. harmonic distortion (second and third) and sfdr vs. a in frequency (1 v p-p, fs = 40 msps) encode rate msps 020 db sinad sfdr 45 60 65 75 40 60 80 100 50 55 70 120 tpc 15. sinad and sfdr vs. encode rate (f in = 10.3 mhz, 105 msps grade) a in = C0.5 dbfs differential, 1 v p-p analog input range 100 0 90 32.5 80 70 60 50 40 30 20 10 0 encode = 65msps a in 1 = 28.1mhz at 7dbfs a in 2 = 29.1mhz at 7dbfs sfdr = 72.9dbfs db tpc 16. two-tone intermodulation distortion (28 mhz, 29 mhz; 1 v p-p, fs = 65 msps) 0 10 20 30 40 50 60 70 80 90 100 db encode = 40msps a in 1 = 10mhz at 7dbfs a in 2 = 11mhz at 7dbfs sfdr = 74dbc 0 20 tpc 17. twoCtone intermodulation distortion (10 mhz, 11 mhz; 1 v p-p, fs = 40 msps) encode rate mhz db 0 102030 40 45 50 55 65 70 75 80 60 50 60 70 80 sinad snr sfdr tpc 18. sinad and sfdr vs. encode rate (a in = 10.3 mhz, 65 msps grade) a in = C0.5 dbfs differential, 1 v p-p analog input range
rev. 0 ad9218 C13C encode positive pulsewidth ns 30 01 db 35 40 45 50 55 60 65 70 75 2345678 sfdr sinad tpc 19. sinad and sfdr vs. encode pulsewidth high. a in = C0.5 dbfs single-ended, 1 v p-p analog input range 105 msps encode clock rate msps 020 ma 140 200 180 160 120 100 80 40 60 80 100 120 140 50 45 40 35 30 25 20 15 10 5 0 iv dd ma iv d -65 -65/-105 iv dd iv d -105 tpc 20. i vd and i vdd vs. encode rate (a in = 10.3 mhz, @ C0.5 dbfs). -65/-105 msps grade cl = 5 pf temperature c v 1.231 1.229 1.227 1.225 1.223 1.221 1.119 40 20 0 20406080 tpc 21. v ref output voltage vs. temperature (i load = 300 a) encode positive pulsewidth ns 75 70 65 60 55 50 45 40 0 4 6 8 10 12 214 db sinad sfdr tpc 22. sinad and sfdr vs. encode pulsewidth high. a in = C0.5 dbfs single ended, 1 v p-p analog input range 65 msps temperature c 4.5 4.0 3.5 3.0 2.5 2.0 40 200 20406080 gain -65 gain -105 % tpc 23. gain error vs. temperature. a in = 10.3 mhz, -65 msps grade, -105 msps grade, 1 v p-p temperature c db 68 66 64 62 60 58 56 54 52 40 200 20406080 sfdr -105 sfdr -65 snr -65 sinad -65 snr -105 sinad -105 tpc 24. snr, sinad, sfdr vs. temperature. a in = 10.3 mhz , -65 msps grade, -105 msps grade, 1 v p-p
rev. 0 ad9218 C14C i load ma 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.0 0.5 0 0.5 1.0 1.5 2.0 1.05 1.00 v 2.5 tpc 25. v ref vs. i load 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 lsb 0 1024 codes tpc 26. typical inl plot. 10.3 mhz a in @ 80 msps a in input level dbfs 90 80 70 60 50 40 30 20 10 0 60 50 40 30 20 10 0 db sfdr dbfs sfdr dbc 70 db ref line snr dbc tpc 27. s fdr vs. a in input level. 10.3 mhz a in @ 80 msps 1.0 0.8 0.6 0.4 0 0.4 0.6 0.8 1.0 lsb 0 1024 codes 0.2 0.2 tpc 28. typical dnl plot. 10.3 mhz a in @ 80 msps
rev. 0 ad9218 C15C theory of operation the ad9218 adc architecture is a bit-per-stage pipeline-type converter utilizing switch capacitor techniques. these stages determine the 7 msbs and drive a 3-bit flash. each stage provides sufficient overlap and error correction allowing opti mization of comparator accuracy. the input buffers are differential, and both sets of inputs are internally biased. this a llows the most flexible use of ac-coupled or dc-coupled and differential or single-ended input modes. the output staging block aligns the d ata, carries out the error correction, and feeds the data to output buffers. the set of output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. there is no discernible difference in performance between the two channels. using the ad9218 encode input any high-speed a/d converter is extremely sensitive to the quality of the sampling clock provided by the user. a track/ hold circuit is essentially a mixer. any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the a/d output. for that reason, considerable care has been taken in the design of the encode input of the ad9218, and the user is advised to give commensurate thought to the clock source. the encode input is fully ttl/cmos-compatible. digital outputs the digital outputs are ttl/cmos-compatible for lower power consumption. during power-down, the output buffers transition to a high impedance state. a data format selection option supports either two s complement (set high) or offset binary output (set low) formats. analog input the analog input to the ad9218 is a differential buffer. for best dynamic performance, impedance at ain and ain should match. special care was taken in the design of the analog input section of the ad9218 to prevent damage and corrup tion of data when the input is overdriven. the nominal input range is 1.024 v p-p. optimum performance is obtained when the part is driven differentially where common mode noise is minimized and even order harmonics are reduced. an example of driving the ad9218 differentially via a wideband rf transformer for ac-coupled applications is shown in figure 12. applications that require dc-coupled differential drive can be accommo- dated using the ad8138 differential output op amp, shown in figure 13. 25 25 0.1 f 1:1 a in a in ad9218 50 analog signal source figure 12. using a wideband transformer to drive the ad9218 10k a in a in ad9218 50 analog signal source 0.1 f 15pf 25 25 500 vocm 500 500 525 5k av dd ad8138 figure 13. using the ad8138 to drive the ad9218 voltage reference a stable and accurate 1.25 v voltage reference is built into the ad9218 (vref out). in normal operation, the internal refer- ence is used by strapping pin 5 (ref in a) and pin 7 (ref in b) to pin 6 (ref out ). the input range for each channel can be adjusted independently by varying the reference voltage inputs applied to the ad9218. no appreciable degradation in per- formance occurs when the reference is adjusted 5%. the full-scale range of the adc tracks reference voltage, which changes linearly. timing the ad9218 provides latched data outputs, with five pipeline delays. data outputs are available one propagation delay (t pd ) after the rising edge of the encode command (see timing dia- gram). the length of the output data lines and loads placed on them should be minimized to reduce transients within the ad9218. these transients can detract from the converter s dynamic performance. the minimum guaranteed conversion rate of the ad9218 is 20 msps. at clock rates below 20 msps, dynamic performance will degrade. user select options two pins are available for a combination of operational modes. these options allow the user to power-down both channels, excluding the reference, or just the b channel. both modes place the output buffers in a high impedance state. recovery from a power-down state is accomplished in 10 clock cycles following power-on. the other option allows the user to skew the b channel output data by one-half a clock cycle. in other words, if two clocks are fed to the ad9218 and are 180 degrees out of phase, enabling the data align will allow channel b output data to be available at the rising edge of clock a. if the same encode clock is pro- vided to both channels and the data align pin is enabled, output data from channel b will be 180 degrees out of phase with respect to channel a. if the same encode clock is provided to both chann els and the data align pin is disabled, both outputs are delivered on the same rising edge of the clock.
rev. 0 ad9218 C16C applications the wide analog bandwidth of the ad9218 makes it attractive for a variety of high-performance receiver and encoder appli- cations. figure 14 shows the dual adc in a typ ical low cost i and q demodulator implementation for cable, satel lite, or wireless lan modem receivers. the excellent dynamic perfor- mance of the adc at higher analog input frequencies and encode rates empowers users to employ direct if sampling techniques. if sampling eliminates or simplifies analog mixer and filter stages to reduce total system cost and power. ad9218 if in 90 vco bpf bpf q adc i adc vco figure 14. typical i/q demodulation scheme evaluation board the ad9218 eval uation board offers an easy way to test the ad9218. it provides a means to drive the analog inputs single- endedly or differentially. differential drive can be tested through a wideband rf transformer or a differential output operational amplifier, the ad8138. the two encode clocks are accessible via on-board smb connectors j2, j7. these clocks are buffered on board to provide the clocks for an on-board dac and latches. the digital outputs and output clocks are available at two 40-pin connectors, p3 and p4. the board has several different modes of operation, and is shipped in the following configuration: differential analog input (rf transformer mode) normal operation timing mode internal voltage reference power connector power is supplied to the board via a detachable 12-pin power strip. +5 v optional supply for operational amplifier 5 v optional supply for operational amplifier v ref a optional external reference input v ref b optional external reference input v dl supply for support logic and dac v dd supply for adc outputs v d supply for adc analog analog inputs the evaluation board accepts a 1 v analog input signal centered at ground at each analog input. smb connectors j4 and j6 are used for a in and b in respectively. these signals each drive a wideband rf transformer t1, t2, allowing the adc performance for differential inputs to be measured using a single-ended source. in this mode resistors r35, r33, r39, and r32 should not be in place. each analog input is terminated on the board with 50 ? to ground. each input is ac-coupled on the board through a 0.1 f capacitor to an on-chip resistor divider that provides dc bias. single-ended performance can be measured by bypassing the transformers using connectors smb j5 (channel a) and j1 (channel b). in this mode, place a 0 ? resistor at r35 and r33 (a channel) and place r39 and r32 (b channel). note that the inverting analog inputs are terminated on the board with 25 ? (optimized for differential operation). when driving the board single-ended these resistors (r1, r3) can be changed to 50 ? to provide balanced inputs. the operational amplifier can be used by connecting to j5 (channel a) and j1 (channel b). the ac- coupling capacitors on the top level should be removed from the board to use the operational amplifier. the compo- nents to use the op amp should be placed on the bottom of the board. see pcb bill of materials list for values. encode the encode clock for channel a uses smb connector j7. channel b encode uses smb connector j2. each clock input is terminated on the board with 50 ? to ground. the input clocks are fed directly to the adc and to buffers u5, u6, which drive the dac and latches. the clock inputs are ttl-compatible. voltage reference the ad9218 has an internal 1.25 v voltage reference. an exter- nal reference for each channel may be employed instead. the evaluation board is configured for the internal reference (use jumpers e18 e1 and e17 e19). to use external references, connect to v ref a and v ref b pins on the power connector p1 and use jumpers e20 e18 and e19 e21. normal operation mode in this mode both converters are clocked by the same encode clock, latency is five clock cycles (see timing diagram). signal s1 (pin 8) is held high and signal s2 (pin 9) is held low. this is set with the jumpers labeled s1 and s2 (near the analog input). data align mode in this mode channel b output is delayed an additional one-half cycle. signals s1 (pin 8) and signal s2 (pin 9) are both held high. this is set with the jumpers labeled s1 and s2 (near the analog input). data format select data format select sets the output data format and the gain of the adc. setting dfs (pin 4) low sets the output format to be offset binary and gain of 1; setting dfs high sets the output to be two s complement and gain of 1. removing the jumper for dfs sets the output data format to offset binary and a gain of 2; setting dfs to the middle selection sets the output data format to two s complement and a gain of 2.
rev. 0 ad9218 C17C pcb bill of materials # qty refdes device package value 1 29 c1, c3 c15, c20 c25, c27 c35 capacitor 0603 0.1 f 2 2 c2, c36 capacitor 0603 15 pf 3 7 c16, c17, c18, c19, c26, c37, c38 capacitor tajd 10 f 6 8 j1, j2, j3, j4, j5, j6, j7, j8 connector smb 7 3 p1, p4, p11 4-pin power connector tb4 wieland 25.531.3425.0 z5.602.5453.0 8 2 p2, p3 header40 10 8 r1 r4, r22 r24, r30 resistor 0603 25 ? 11 10 r5 r12, r34, r37 resistor 0603 50 ? 12 2 r13, r14 resistor 0603 2 k ? 13 6 r15, r17, r18, r26, r29, r31 resistor 0603 500 ? 14 2 r16, r25 resistor 0603 525 ? 15 2 r19, r27 resistor 0603 4 k ? 16 8 r20, r32, r33, r35, r36, r38 r40 resistor 0603 0 ? 17 2 r21, r28 resistor 0603 1 k ? 18 2 t1, t2 transformer adt-1-1wt minicircuits 19 1 u1 ad9218 lqfp48 20 2 u2, u3 74lcx821 so24m3 21 1 u4 ad9763 lqfp48 22 2 u5, u6 74lcx86 so14 23 4 u7, u8, u9, u10 resistor array cts20 22 ? 24 2 u11, u12 ad8138 so8nb note r22, r23, r24, r30, r32, r33, r35, r36, r38, r39, r40, c2, c36 not placed on board. data outputs the adc digital outputs are latched on the board by two lcx821s, the latch outputs are available at the two 40-pin connectors at pins 23 33 on p3 (channel a) and pins 23 33 on p4 (channel b). the latch output clocks (data ready) are avail- able at pin 4 on p3 (channel a) and pin 4 on p4 (channel b). the data ready signal on channel b can be aligned with clock a input by connecting e43 e42 or aligned with clock b input by connecting e42 e33. ch1 2.00v ch2 2.00v m 10.0ns ch4 40mv pin 31 (data) pin 37 (clock) t figure 15. data output and clock at 80-pin connector dac outputs each channel is reconstructed by an on-board dual channel dac, an ad9763. this dac is intended to assist in debug only. it should not be used to measure the performance of the adc. it is a current output dac with on-board 50 ? termination resistors. figure 16 is representative of the dac output with a full-scale analog input. the scope setting was low bandwidth, 50 ? termination. ch1 500mv m 50.0ns ch1 380mv 1 t figure 16. dac output
rev. 0 ad9218 C18C 1a 1b 1y 2a 2b 2y gnd 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v cc 4b 4a 4y 3b 3a 3y u5 74lcx86 gnd c13 0.1 f v dl v dl v dl clklatb e5 e44 e4 gnd e15 e11 e12 gnd clkdacb p23 tieb p22 enc b p20 p21 enc b e13 e16 e14 j2 encode b gnd gnd r7 50 e49 e48 e50 gnd v dl gnd v dl tieb gnd drb dut clock selectable to be direct or buffered 1a 1b 1y 2a 2b 2y gnd 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v cc 4b 4a 4y 3b 3a 3y u8 74lcx86 gnd c25 0.1 f v dl v dl v dl clkdaca e40 e41 e3 gnd e39 e38 e37 gnd dra p13 tiea p14 enc a p12 p19 enc a e35 e36 e34 j7 encode a gnd gnd r11 50 e46 e45 e47 gnd v dl gnd v dl tiea gnd clklata dut clock selectable to be direct or buffered gnd 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 ad9218 u1 gnd a in a a in ab dfs/gain ref in a ref out ref in b s1 s2 a in b a in b gnd v d enc a v dd gnd d9a d8a d7a d6a d5a d4a d3a d2a v d enc b v dd gnd d9b d8b d7b d6b d5b d4b d3b d2b d1a d0a gnd v dd gnd v d v d gnd v dd gnd d0b d1b e1 e18 e20 e17 vrefa vrefb e19 e21 e30 a in ab gnd a in a ref out e2 e27 e25 gnd gnd e29 e22 e28 e26 gnd v d gnd gnd 6 5 4 gnd 1 2 3 c31 0.1 f 6 5 4 gnd 1 2 3 c30 0.1 f gnd gnd c10 0.1 f c9 0.1 f c12 0.1 f r1 25 r2 25 r4 25 c11 0.1 f r3 25 r32 0 r39 0 gnd gnd j5 a in a single-ended gnd j4 a in a differential gnd j6 a in b differential gnd j1 a in b single-ended gnd c37 10 f 5v c38 10 f v d c16 10 f v dd c17 10 f v dl c18 10 f vrefa c19 10 f c26 10 f vrefb +5v 4 gnd 3 +5v 2 5v 1 gnd p11 p4 p1 4 gnd 3 gnd 2 vrefa 1 vrefb 4 v d 3 v dd 2 1 gnd v dl gnd d0b d1b c1 0.1 f v dd gnd c3 0.1 f gnd gnd gnd v d gnd d1a d0a gnd c4 0.1 f v dd gnd gnd d9a d8a d7a d6a d5a d4a d3a d2a gnd c8 0.1 f gnd c7 0.1 f v d enc a v dd gnd c5 0.1 f gnd c6 0.1 f v d enc b v dd gnd d9b d8b d7b d6b d5b d4b d3b d2b c24 0.1 f gnd ref in b c27 0.1 f gnd ref in a h3 mt hole6 gnd h1 mt hole6 h2 mt hole6 h4 mt hole6 e9 v d e10 v dd e32 v dd e31 v dl optional input path for opamp or single-ended optional input path for opamp or single-ended a in b a in bb v d v d e23 e24 c15 0.1 f gnd r6 50 c14 0.1 f gnd r5 50 t2 r33 00 r35 00 amp in a r36 0 gnd r34 50 amp in b r38 0 gnd r37 50 t1 figure 17a. pcb schematic
rev. 0 ad9218 C19C 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 ct520 value = 22 gnd c21 0.1 f d9a d8a d7a d6a d5a d4a d3a d2a d1a d0a d9m d8m d7m d6m d5m d4m d3m d2m d1m d0m gnd x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 gnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v cc y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 clk 74lcx821 gnd d9m d8m d7m d6m d5m d4m d3m d2m d1m d0m gnd v dl d9x d8x d7x d6x d5x d4x d3x d2x d1x d0x clklata u2 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 ct520 value = 22 d9x d8x d7x d6x d5x d4x d3x d2x d1x d0x d9p d8p d7p d6p d5p d4p d3p d2p d1p d0p 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 header40 gnd dra gnd d9p d8p d7p d6p d5p d4p d3p d2p d1p d0p gnd gnd gnd gnd gnd gnd gnd p3 gnd 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 u7 u9 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 ct520 value = 22 e7 e6 e8 drb gnd c20 0.1 f d0b d1b d2b d3b d4b d5b d6b d7b d8b d9b d0n d1n d2n d3n d4n d5n d6n d7n d8n d9n oe x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 gnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v cc y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 clk 74lcx821 gnd d0n d1n d2n d3n d4n d5n d6n d7n d8n d9n gnd v dl d0y d0y d0y d0y d0y d0y d0y d0y d0y d0y u3 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 ct520 value = 22 d0y d1y d2y d3y d4y d5y d6y d7y d8y d9y d0q d1q d2q d3q d4q d5q d6q d7q d8q d9q 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 header40 gnd gnd d9q d8q d7q d6q d5q d4q d3q d2q d1q d0q gnd gnd gnd gnd gnd gnd gnd p2 dra gnd 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 e42 e33 e43 clklata clklatd u8 u10 figure 17b. pcb schematic
rev. 0 ad9218 C20C 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 9763 db8 p1 db7 p1 db6 p1 db5 p1 db4 p1 db3 p1 db2 p1 db1 p1 db0 p1 nc nc1 mode av dd ia2 ib1 fsadj1 refio reflo fsadj2 ib2ia2 acom sleep nc2 nc3 gnd dcom1 dv dd wrt1/iqwrt clk1/iqclk clk2/iqreset wrt2/iqsel dcom2 db9 p2 nc7 nc6 nc5 nc4 db0 p2 db1 p2 db2 p2 db3 p2 db4 p2 db5 p2 db6 p2 db7 p2 d0y c23 0.1 f v dl c22 0.1 f gnd c28 0.1 f d1y d2y d3y d4y d5y d6y d7y d8y d9y d0x d1x d2x d3x d4x d5x d6x d7x gnd v dl gnd r10 50 j3 gnd gnd r12, 50 gnd r13, 2k gnd gnd r14, 2k gnd r8, 50 gnd gnd r9 50 gnd j8 dac output a dac output b gnd v dl gnd c29 0.1 f d8x d9x v dl gnd gnd gnd clkdacb clkdacb clkdaca clkdaca gnd u4 nc = no connect db8 p2 db9 p1 gnd r20 00 v dl r40 00 power-down option ad8138 in vocm v+ +out +in nc v out 1 2 3 4 8 7 6 5 r19 4k r21 1k +5v c32 0.1 f gnd r22 25 r23 25 c2 15pf u11 5v c33 0.1 f amp in a gnd r17 500 r16 525 gnd a in a ai in ab gnd 5v r15 500 r18 500 nc = no connect ad8138 in vocm v+ +out +in nc v out 1 2 3 4 8 7 6 5 r27 4k r28 1k +5v c35 0.1 f gnd r30 25 r24 25 c36 15pf u12 5v c34 0.1 f amp in b gnd r29 500 r25 525 gnd a in bb a in b gnd 5v r31 500 r26 500 nc = no connect (optional) figure 17c. pcb schematic
rev. 0 ad9218 C21C figure 18. pcb top side silkscreen figure 19. pcb top side copper
rev. 0 ad9218 C22C figure 20. pcb ground layer figure 21. pcb split power plane
rev. 0 ad9218 C23C figure 22. pcb bottom side copper figure 23. bottom side silkscreen
rev. 0 C24C c02001C1.5C7/01(0) printed in u.s.a. ad9218 48-lead lqfp (st-48) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0 min coplanarity 0.003 (0.08) seating plane 0.006 (0.15) 0.002 ( 0.05 ) 7 0 0.057 (1.45) 0.053 (1.35) outline dimensions dimensions shown in inches and (mm). troubleshooting if the board does not seem to be working correctly, try the following: verify power at ic pins. check that all jumpers are in the correct position for the desired mode of operation. verify v ref is at 1.23 v. try running encode clock and analog inputs at low speeds (20 msps/1 mhz) and monitor lcx821 outputs, dac outputs, and adc outputs for toggling. the ad9218 evaluation board is provided as a design example for custom ers of analog devices, i nc. adi makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.

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